1. Field of the Invention
The present invention relates to a semiconductor integrated circuit containing a circuit block (first circuit block) incorporating a technology for reducing power consumption during an inactive period such as so-called MTCMOS and to an operation method of the same for activating the first circuit block.
2. Description of the Related Art
Much headway has been made in reducing the source voltage of CMOS integrated circuits due to increased packaging density and finer patterning achieved in recent years. Source voltage reduction is required not only to ensure reliability as a result of finer patterning but also to reduce power consumption. However, reduced source voltage leads to lower operation speed of MOS transistors. As a result, the CMOS transistor threshold voltage must be lowered to provide improved operation speed and secure a sufficient operational margin. In the case of today's LSIs having a minimum feature size of 100 nm or less, for example, a source voltage Vdd must be reduced to around 1.0 V. In this case, the transistor threshold voltage must be lowered to about 0.3 V.
As is well known, however, increased leak current in the sub-threshold region as a result of the reduction in threshold voltage is problematic. It is therefore essential how to reduce this leak current.
In light of the above, MTCMOS (Multi-threshold Complementary Metal Oxide Semiconductor) has been proposed as a contrivance in circuit configuration in addition to process approaches including improving the leak characteristic and increasing the operational speed, for example, by reducing the parasitic capacitance.
A logic LSI made up of MTCMOSs includes a logic circuit block and switching transistor. The logic circuit block is connected between a virtual source voltage supply line (hereinafter referred to as the “V-Vdd line”) and a virtual reference voltage supply line (hereinafter referred to as the “V-Vss line”). The switching transistor is connected between the V-Vdd line and a source voltage supply line (Vdd line) or between the V-Vss line and a reference voltage supply line (Vss line). The switching transistor is on when the logic circuit block is active and off when the logic circuit block is not active. Alternatively, the switching transistor may be provided either between the V-Vdd and Vdd lines or between the V-Vss and Vss lines.
The switching transistor has a higher threshold voltage and handles larger power than the logic transistor of the logic circuit. For this reason, this transistor is also called a power gate transistor.
In the logic circuit block incorporating the MTCMOS technology, a potential difference develops in the virtual power line such as the V-Vdd or V-Vss line according to the operational status of the logic circuit cells making up the logic circuit block. A potential difference changes the delay characteristic of the logic circuits, making it necessary to address this change, for example, by increasing the design margin. This restricts improvement in circuit characteristics.
To overcome this disadvantage, the applicant of the present embodiment applied, for a patent, an embodiment for providing a switching transistor for each logic circuit. The embodiment is disclosed in a Japanese Patent Laid-open No. 2005-183681 (hereinafter referred to as Patent Document 1).